/////////////////////////////////////////////
/////////Designer Dup
////////Description
module	sram_mux(
	//input
	clk_1m,
	rst_n,
	down_link_req,
	up_link_req,
	sram_mux,
	//sram_data,
	sram_ack,
	down_sram_wr,
	down_sram_rd,
	down_sram_addr,
	down_sram_data,
	//down_wr_sram_req,
	up_sram_wr,
	up_sram_rd,
	up_sram_addr,
	up_sram_data,
	
	//output
	sram_rd,
	sram_wr,
	sram_addr,
	sram_data_out
);
parameter N = 8;
input clk_1m,
	  rst_n,
	  down_link_req,
	  up_link_req,
	  sram_mux;
//input [N-1:0] sram_data;
input sram_ack;
input down_sram_wr,down_sram_rd;
input [12:0] down_sram_addr;
input [N-1:0] down_sram_data;
//input down_wr_sram_req;
input up_sram_wr,up_sram_rd;
input [12:0] up_sram_addr;
input [N-1:0] up_sram_data;


output sram_rd;
output sram_wr;
output [12:0]sram_addr;
output [N-1:0]sram_data_out;

//reg sram_mux;///为1的时候表示up_link对sram进行操作
			///为0的时候表示down_link对sram进行操作
			
			
			
assign sram_rd       =  sram_mux ? up_sram_rd   : down_sram_rd;
assign sram_wr       =  sram_mux ? up_sram_wr   : down_sram_wr;
assign sram_addr     =  sram_mux ? up_sram_addr : down_sram_addr;
assign sram_data_out =  sram_mux ? up_sram_data : down_sram_data;


// always@(posedge clk_1m or negedge rst_n)
// if(!rst_n)
	// sram_mux <= 1'b1;
// else 
	// begin
		// case(sram_mux)
		// 1'b0: begin if(down_link_req) sram_mux <= 1'b1;end
		// 1'b1: begin if(up_link_req)   sram_mux <= 1'b0;end
		// endcase
	// end

endmodule 




